ATmega328P Memory

Below is an overview of ATmega328P memory summarized from the datasheet. ATmega328P uses harvard architecture where (1) program and (2) data reside in separate memories.

(1) Program Memory

• Contains 16- or 32-bit instructions, constant tables, and interrupt vector table.
• Physically implemented as flash memory.
• Divided into application and boot loader sections (each with dedicated lock bits for read and read/write protection).

Interrupt table is an array of interrupt vectors. Interrupt vector is a 16-bit memory that contains the address of the corresponding interrupt routine, ISR. All interrupts have a separate interrupt vector.

By default, the interrupt table is stored at the top (lowest address) of the program memory. Interrupts with lower interrupt vector addresses have higher priority. For example, RESET has the highest priority and next is INT0.

The interrupt table can be moved to the start of the boot loader, by

• Setting the IVSEL bit in the MCU control register (MCUCR), or
• Programming the BOOTRST fuse.

Also referred as: flash memory, program memory space, program flash memory, program flash memory space, in-system reprogrammable flash memory.

Application

Code stored in program memory.

Also referred as: application program, application section.

Boot Loader

Code stored in program memory that can execute SPM instruction to write application code to program memory. Arduino uses the boot loader to flash new code without the need for special hardware (i.e. programmer).

Also referred as: boot program, boot flash, boot loader section, BLS, boot loader flash section.

(2) Data Memory

Also referred as: SRAM, data memory space, user data space, data space.

General Purpose Registers

First 32 bytes in data memory.

• 32 8-bit registers, R0 to R31.
• Last six registers, R26 to R31, can be used as three 16-bit registers (X-, Y-, and Z-registers) to store addresses (for using them as pointers).
• Not physically implemented as SRAM (although address continues through data memory).

Also referred as: general purpose working registers, register file, general purpose register file.

I/O Space

64 bytes in data memory for CPU peripheral functions (via control registers), SPI, and other I/O functions.

Interrupt control registers and status register (which contains global interrupt enable bit) are in the I/O space. I/O space also contains three general purpose I/O registers (GPIOR0, GPIOR1, GPIOR2) for storing global variables and status flags.

Restrictions:

• CBI/SBI and SBIS/SBIC (bit access) works on I/O addresses 0x00 to 0x1F.
• IN/OUT works on I/O addresses 0x00 to 0x3F.
• ST/STS/STD and LD/LDS/LDD works on addresses 0x0020 to 0x00FF.

Reserved bits should be written to zero if accessed for compatibility with future devices. Reserved I/O memory addresses should not be written.

Also referred as: I/O memory, I/O memory space.

Status Register

A byte in I/O space that contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Status register is updated after all ALU operations. This can remove the need for using dedicated compare instructions.

Status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by user program.

Also referred as: SREG.

Global Interrupt Enable Bit

7th bit (I-bit) in the status register used for enabling and disabling interrupts.

• Set (write logic one) = enable
• Clear (write logic zero) = disable

Interrupt routine is called if

• I-bit is set AND
• That interrupt's enable control bit is also set.

When an interrupt occurs, the hardware

1. Clears the I-bit (disables all interrupts), then
2. Sets the I-bit on return by RETI instruction (enables subsequent interrupts)

The I-bit can be set and cleared by user program with the SEI and CLI instructions. Setting it enables nested interrupts.

Extended I/O Space

Only ST/STS/STD and LD/LDS/LDD instructions can be used.

Internal SRAM

Also referred as: data SRAM, internal data SRAM, general data SRAM.

Stack

Data allocated in internal SRAM for storing temporary data, local variables, and return addresses after interrupts and subroutine calls. When interrupts and subroutine calls are executed, the return address is stored on the stack. Stack grows from higher to lower memory locations. Stack size is limited by the total SRAM size and the usage of the SRAM.

When an interrupt occurs, the program counter (14-bit memory that contains the address of the currently executing instruction) is pushed onto the stack. Upon return, the program counter is popped back from the stack (2 bytes).

Stack Pointer

16-bit register in I/O space. Composed of two 8-bit registers, SPL and SPH. Points to (contains the address of) the top of the stack, which is in the data SRAM stack area where the subroutine and interrupt stacks are located.

Instructions:

• PUSH (decrement SP by 1): push data onto the stack.
• POP (increment SP by 1): pop data from the stack.
• CALL/ICALL/RCALL (decrement SP by 2): push return address onto the stack with subroutine call or interrupt.
• RET/RETI (increment SP by 2): pop return address from the stack with return from subroutine or return from interrupt.

User program must initialize the stack pointer to 0x08FF (the last address of the internal SRAM) in the reset routine before any subroutine calls are executed or interrupts are executed.

Also referred as: stack pointer register, SP.